Active 1:N breakout cable

ABSTRACT

Accordingly, there are disclosed herein active cables and methods that enable direct connection between different generations of network interface ports or ports supporting different standards. One illustrative embodiment is an active 1:N breakout cable that includes a unary end connector connected by electrical conductors to each of multiple split end connectors. The unary end connector is adapted to fit into a network interface port of a primary host device to provide output PAM4 electrical signals that convey a multi-lane outbound data stream to the primary host device and to accept input PAM4 electrical signals that convey multi-lane inbound data stream from the primary host device. Each of the split end connectors is adapted to fit into a network interface port of a secondary host device to provide output NRZ electrical signals that convey a split portion of the inbound data stream to that secondary host device and to accept input NRZ electrical signals that convey a split portion of the outbound data stream from that secondary host device.

BACKGROUND

The Institute of Electrical and Electronics Engineers (IEEE) StandardsAssociation publishes an IEEE Standard for Ethernet, IEEE Std802.3-2015, which will be familiar to those of ordinary skill in the artto which this application pertains. This Ethernet standard provides acommon media access control specification for local area network (LAN)operations at selected speeds from 1 Mbps to 100 Gbps over coaxialcable, twinaxial cable, twisted wire pair cable, fiber optic cable, andelectrical backplanes, with various channel signal constellations. Asdemand continues for ever-higher data rates, the standard is beingextended. Such extensions to the standard must account for increasedchannel attenuation and dispersion even as the equalizers are forced tooperate at faster symbol rates. As the standard is extended, however, itmay not be directly inter-operable with the current-generation. Forexample, there exists no way to directly couple current generation 100Gbps Ethernet ports to proposed next generation 400 Gbps Ethernet ports.

SUMMARY

Accordingly, there are disclosed herein active cables and methods thatenable direct connection between different generations of networkinterface ports or ports supporting different standards. Oneillustrative embodiment is an active 1:N breakout cable that includes aunary end connector connected by electrical conductors to each ofmultiple split end connectors. The unary end connector is adapted to fitinto a network interface port of a primary host device to provide outputPAM4 electrical signals that convey a multi-lane outbound data stream tothe primary host device and to accept input PAM4 electrical signals thatconvey multi-lane inbound data stream from the primary host device. Eachof the split end connectors is adapted to fit into a network interfaceport of a secondary host device to provide output NRZ electrical signalsthat convey a split portion of the inbound data stream to that secondaryhost device and to accept input NRZ electrical signals that convey asplit portion of the outbound data stream from that secondary hostdevice.

Another illustrative embodiment is a cable manufacturing method thatincludes: packaging a transceiver into a unary end connector that isadapted to mate with a network interface port of a primary host device;and connecting each of multiple split end connectors to the unary endconnector with electrical conductors. Each of the split end connectorsis adapted to mate with a network interface port of a secondary hostdevice to provide output NRZ electrical signals that convey a splitportion of a multi-lane inbound data stream to that secondary hostdevice and to accept input NRZ electrical signals that convey a splitportion of a multi-lane outbound data stream from that secondary hostdevice. The transceiver is configured to provide output PAM4 electricalsignals that convey the outbound data stream to the primary host deviceand to accept input PAM4 electrical signals that convey the inbound datastream from the primary host device. The transceiver is furtherconfigured to perform clock and data recovery on the input PAM4electrical signals to extract and re-modulate the inbound data stream asdiverging transit signals that transport the split portions of theinbound data stream via the electrical conductors to the split endconnectors, and to perform clock and data recovery on converging transitsignals to extract and re-modulate the outbound data stream as saidoutput PAM4 electrical signals.

Yet another illustrative embodiment is a cable manufacturing method thatincludes: packaging a transceiver into each of multiple split endconnectors adapted to mate with a network interface port of a secondaryhost device; and connecting each of the split end connectors to a unaryend connector via electrical conductors. The unary end connector isadapted to mate with a network interface port of a primary host deviceto provide output PAM4 electrical signals that convey a multi-laneoutbound data stream to the primary host device and to accept input PAM4electrical signals that convey a multi-lane inbound data stream from theprimary host device. Each of the transceivers in the split endconnectors is configured to provide output NRZ electrical signals thatconvey a split portion of the inbound data stream to that secondary hostdevice and to accept input NRZ electrical signals that convey a splitportion of the outbound data stream from that secondary host device. Thetransceiver in each split end connector is further configured to performclock and data recovery on the input NRZ electrical signals to extractand re-modulate the split portion of the outbound data stream asconverging transit signals that transport the split portions of theoutbound data stream via the electrical conductors to the unary endconnector, and to perform clock and data recovery on diverging transitsignals to extract and re-modulate the split portion of the inbound datastream as said output NRZ electrical signals.

Still another illustrative embodiment is an active 1:N breakout cablethat includes a unary end connector connected by electrical conductorsto each of N split end connectors, N being an integer greater than 1.The unary end connector is adapted to fit into a network interface portof a primary host device to provide first output electrical signals thatconvey a multi-lane outbound data stream to the primary host device at afirst symbol rate and to accept first input electrical signals thatconvey multi-lane inbound data stream from the primary host device atthe first symbol rate. Each of the split end connectors is adapted tofit into a network interface port of a secondary host device to providesecond output electrical signals that convey a split portion of theinbound data stream to that secondary host device at a second symbolrate and to accept second input electrical signals that convey a splitportion of the outbound data stream from that secondary host device atthe second symbol rate, the second symbol rate being half of the firstsymbol rate.

Still yet another illustrative embodiment is a cable manufacturingmethod that includes: packaging a transceiver into a unary end connectorthat is adapted to mate with a network interface port of a primary hostdevice; and connecting each of N split end connectors to the unary endconnector with electrical conductors, where N is an integer greater thanone. Each of the split end connectors is adapted to mate with a networkinterface port of a secondary host device to provide second outputelectrical signals that convey a split portion of the inbound datastream to that secondary host device at a second symbol rate and toaccept second input electrical signals that convey a split portion ofthe outbound data stream from that secondary host device at the secondsymbol rate. The transceiver is configured to provide first outputelectrical signals that convey a multi-lane outbound data stream to theprimary host device at a first symbol rate and to accept first inputelectrical signals that convey multi-lane inbound data stream from theprimary host device at the first symbol rate that is twice the secondsymbol rate. The transceiver is further configured to perform clock anddata recovery on the first input electrical signals to extract andre-modulate the inbound data stream as diverging transit signals thattransport the split portions of the inbound data stream via theelectrical conductors to the split end connectors, and to perform clockand data recovery on converging transit signals to extract andre-modulate the outbound data stream as said first output electricalsignals.

Yet still another illustrative embodiment is a cable manufacturingmethod that includes: packaging a transceiver into each of N split endconnectors adapted to mate with a network interface port of a secondaryhost device, where N is an integer greater than one; and connecting eachof the split end connectors to a unary end connector via electricalconductors. The unary end connector is adapted to mate with a networkinterface port of a primary host device to provide unary end outputelectrical signals that convey the outbound data stream to the primaryhost device at a first symbol rate and to accept unary end inputelectrical signals that convey the inbound data stream from the primaryhost device at the first symbol rate. Each of the transceivers in thesplit end connectors is configured to provide split end outputelectrical signals that convey a split portion of a multi-lane inbounddata stream to that secondary host device at a second symbol rate thatis half the first symbol rate and to accept split end input electricalsignals that convey a split portion of a multi-lane outbound data streamfrom that secondary host device at the second symbol rate. Each of thetransceivers is further configured to perform clock and data recovery onthe split end input electrical signals to extract and re-modulate thesplit portion of the outbound data stream as converging transit signalsthat transport the split portions of the outbound data stream via theelectrical conductors to the unary end connector, and to perform clockand data recovery on diverging transit signals to extract andre-modulate the split portion of the inbound data stream as said splitend output electrical signals.

Each of the foregoing embodiments may be implemented individually or incombination, and may be implemented with one or more of the followingfeatures in any suitable combination: 1. the unary end connectorincludes a transceiver that performs clock and data recovery on theinput PAM4 electrical signals to extract and re-modulate the inbounddata stream as diverging transit signals that transport the splitportions of the inbound data stream via the electrical conductors to thesplit end connectors. 2. the transceiver in the unary end connectorperforms clock and data recovery on converging transit signals toextract and re-modulate the outbound data stream as said output PAM4electrical signals. 3. the diverging transit signals and the convergingtransit signals are NRZ electrical signals. 4. the diverging transitsignals and the converging transit signals are PAM4 electrical signals.5. each of the split end connectors includes a redriver circuit thatprovides the output NRZ electrical signals by amplifying the divergingtransit signals that it receives. 6. the redriver circuit provides atleast one of the converging transit signals by amplifying the input NRZelectrical signals that it receives. 7. each of the split end connectorsincludes a transceiver that performs clock and data recovery on thediverging transit signals that it receives to extract and re-modulatethe split portion of the inbound data stream. 8. the transceiver in eachsplit end connector performs clock and data recovery on the input NRZelectrical signals to extract and re-modulate the split portion of theoutbound data stream. 9. the transceiver in each split end connectorfurther performs forward error correction when extracting the splitportion of the inbound data stream. 10. the transceiver in the unary endconnector further performs forward error correction when extracting theoutbound data stream. 11. packaging a redriver circuit into each of thesplit end connectors. 12. packaging a transceiver into each of the splitend connectors. 13. packaging a transceiver in the unary end connector.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of an illustrative active 1:N breakoutcable.

FIG. 2A is schematic view of one illustrative breakout cable embodiment.

FIG. 2B is schematic view of a second illustrative breakout cableembodiment.

FIG. 3A is a function-block diagram of an illustrative gearboxtransceiver embodiment.

FIG. 3B is a function-block diagram of an illustrative CDR transceiverembodiment.

FIG. 4 is a block diagram of an illustrative receiver.

FIG. 5 is a block diagram of an illustrative transmitter.

FIG. 6 is an architecture diagram for an active cable connector.

FIG. 7 is a flow diagram of an illustrative cable manufacturing method.

DETAILED DESCRIPTION

While specific embodiments are given in the drawings and the followingdescription, keep in mind that they do not limit the disclosure. On thecontrary, they provide the foundation for one of ordinary skill todiscern the alternative forms, equivalents, and modifications that areencompassed in the scope of the appended claims.

FIG. 1 is a perspective view of an illustrative 1:4 breakout cable thatmay be used to provide a high-bandwidth communications link betweendevices in a routing network. The routing network may be or include, forexample, the Internet, a wide area network, or a local area network. Thelinked devices may be computers, switches, routers, hubs, and the like.The breakout cable includes unary end connector 100 electricallyconnected via conductors 106 to multiple split end connectors 101-104.The unary end may also be referred to, among other things, as the commonend, the unsplit end, or the primary host end, and it is designed tocommunicate with the network interface of a host at N times the datarate of the split end connectors, where N is the number of split endconnectors. The split end connectors may be referred to, among otherthings, as the breakout end, divided end, legacy end, or secondary hostend, and it is designed to communicate with the network interface of ahost at 1/N times the data rate of the unary end connector.

The electrical conductors may be provided in a paired form such as withtwinaxial conductors. Twinaxial conductors can be likened to coaxialconductors, but with two inner conductors instead of one. The innerconductors may be driven with a differential signal and their sharedshield operates to reduce crosstalk with other twinaxial conductors inthe cable. Depending on the performance criteria, it may be possible toemploy other paired or single-ended conductor implementations. Pairedconductors may provide unidirectional transport of a differentialsignal.

In one contemplated 1:4 breakout cable embodiment, the unary endconnector is a quad small form factor pluggable double density (QSFP-DD)connector or an octal small form factor pluggable (OSFP) connectorconfigured to provide and accept 400 Gbps in the form of 8 lanes of 50Gbps PAM4 electrical signals. The four split end connectors are quadsmall form factor pluggable rated up to 28 Gbps/lane (QSFP28)connectors, each configured to provide and accept 100 Gbps in the formof 4 lanes of 25 Gbps NRZ electrical signals. Thus, this contemplatedembodiment includes a “gearbox” module that converts between 50 GbpsPAM4 electrical signals and 25 Gbps NRZ electrical signals. However, anyconnector that complies with the Ethernet standard or other networkcommunications standard may be used.

In another contemplated 1:2 breakout cable embodiment, the unary endconnector is configured to provide and accept 400 Gbps in the form of 4lanes of 100 Gbps PAM4 electrical signals. The two split end connectorsare each configured to provide and accept 200 Gbps in the form of 4lanes of 50 Gbps PAM4 electrical signals. Thus, this contemplatedembodiment includes a gearbox module that converts between lane pairs of50 Gbps PAM4 electrical signals and individual lanes of 100 Gbps PAM4electrical signals.

In yet another contemplated 1:2 breakout cable embodiment, the unary endconnector is configured to provide and accept 80 Gbps in the form of 4lanes of 20 Gbps NRZ electrical signals. The two split end connectorsare each configured to provide and accept 40 Gbps in the form of 4 lanesof 10 Gbps NRZ electrical signals. Thus, this contemplated embodimentincludes a gearbox module that converts between lane pairs of 10 GbpsNRZ electrical signals and individual lanes of 20 Gbps NRZ electricalsignals.

To provide PAM4-NRZ and/or 2-to-1 lane+rate conversion while enablingrobust performance, the unary end connector and/or the split endconnectors may include a powered transceiver that performs clock anddata recovery (CDR) and re-modulation of data streams in each direction.Notably, the transceiver would perform CDR and re-modulation not only ofthe outbound data streams as they exit the cable, but also of theinbound data streams as they enter the cable. (Though used here for bothunary and split end connectors, the terms “inbound” and “outbound” asused in the claims will be defined with respect to the unary endconnector 100, such that the “inbound” data stream is the data streamentering the cable at the unary end connector and gets divided among thesplit end connectors where split portions of the inbound data streamexit the cable. Conversely, the “outbound” data stream is the datastream exiting the cable at the unary end connector after beingassembled from split portions that have entered the cable at the splitends.)

It is acknowledged here that the data streams entering the cable may beexpected to be compliant with the relevant standard and may be expectedto have experienced essentially no deterioration from their traversal ofthe network interface port's receptacle pins and the connector's plugpins. Nevertheless, the modulation quality and equalization strategyemployed by the electronics manufacturer of the transmitting networkinterface is generally unknown and the minimum requirements of thestandard may be inadequate for transport over an extended cable length,particularly if the electronics manufacturer of the receiving networkinterface is different than that of the transmitting network interface.As with the transmitting network interface, the equalization anddemodulation strategy employed by the electronics manufacturer of thereceiving network interface is generally unknown and may be unable tocope with the attenuation and interference caused by signal transportover an extended cable length. At least some of the contemplatedembodiments perform CDR and re-modulation of both entering and exitingdata streams at each end to assure consistently robust data transferover even extended cable lengths without consideration of theelectronics manufacturers of the network interfaces.

FIG. 2A is a schematic view of one contemplated active 1:4 breakoutcable embodiment. An integrated circuit TR0 is packaged in the unary endconnector 100, while each of the split end connectors 101-104 includes arespective integrated circuit TR1-TR4. Integrated circuit TR0 may besoldered to a printed circuit board that connects a host-facing side ofthe integrated circuit to the pins of the unary end connector 100 and acable-facing side of the integrated circuit to the electrical conductors106. Similarly each of the integrated circuits TR1-TR4 may be solderedto a printed circuit board that connects the host-facing sides of theintegrated circuits to the pins of the split end connectors 101-104 andthe cable-facing sides of the integrated to the electrical conductors106. In at least some embodiments, all of the integrated circuitsTR0-TR4 are transceivers that perform CDR and re-modulation of datastreams traveling in both directions. In other embodiments, eitherintegrated circuit TR0 or integrated circuits TR1-TR4 are redrivers(analog linear amplifiers) that operate on signals that have beenattenuated during transport over the conductors 106, and which mayfurther operate on signals about to be transmitted over the conductorsto pre-compensate for at least some of that attenuation. In still otherembodiments, either integrated circuit TR0 or integrated circuitsTR1-TR4 are omitted in favor of direct connections between theconductors 106 and the connector pins.

FIG. 2A shows a contemplated cable embodiment in which the unary endconnector 100 includes a transceiver TR0 with a gearbox module. Thehost-facing side of the transceiver TR0 provides and accepts 8 lanes of50 Gbps PAM4 electrical signals. The cable-facing side of thetransceiver TR0 provides and accepts 16 lanes of 25 Gbps NRZ electricalsignals. The 16 lanes are apportioned four-apiece to the split endconnectors 101-104. A potential advantage of this embodiment is that the25 Gbps NRZ electrical signals may tolerate attenuation and interferencebetter than 50 Gbps PAM4 signals, thereby providing more robustperformance and potentially enabling the use of redrivers or directconnections in the split end connectors 101-104. Alternatively, theintegrated circuits TR1-TR4 may be transceivers that accept and provide4 lanes of 25 Gbps NRZ electrical signals on both the host-facing andcable-facing sides.

FIG. 2B shows an alternative cable embodiment in which the split endconnectors 101-104 each include a transceiver (TR1′-TR4′) having a gearbox module. The host-facing sides of the transceivers TR1-TR4 provideand accept 4 lanes of 25 Gbps NRZ electrical signals. The cable-facingsides of these transceivers provide and accept 2 lanes of 50 Gbps PAM4electrical signals, which combine to supply the unary end connector with8 lanes of 50 Gbps PAM4 electrical signals. A potential advantage ofthis embodiment is that it requires fewer conductors 106. Greater costsavings may be further achieved by using a redriver or directconnections in the unary end connector 100. Alternatively, theintegrated circuit TR0′ may be a transceiver that accepts and provides 8lanes of 50 Gbps NRZ electrical signals on both the host-facing andcable-facing sides.

FIG. 3A is a function block diagram of an illustrative transceiver thatincludes gearbox functionality. The transceiver includes a first set oftransmitters and receivers 302 and a second set of transmitters andreceivers 304. In FIG. 3A, the first set 302 is for high-rate lanes(e.g., 50 Gbps PAM4) and the second set 304 is for low-rate lanes (e.g.,25 Gbps NRZ). The gearbox functionality is provided by a set 306 offormat converters. In FIG. 3A, set 306 is shown as including PAM4-to-NRZconverters and NRZ-to-PAM4 converters. The PAM4-to-NRZ converters eachaccept a data stream of PAM4 symbols produces two NRZ bit streams. In atleast some embodiments, the PAM4-to-NRZ converters decode the PAM4symbols using Gray coding to obtain the corresponding data bits, andallocate one bit from each symbol to each NRZ bit stream. Conversely,the NRZ-to-PAM4 converters each accept two NRZ bit streams and convertthem to a data stream of PAM4 symbols. The NRZ-to-PAM4 converters take abit from each bit stream and apply Gray coding to obtain each PAM4symbol.

In other contemplated embodiments, the set 306 of format converters maybe multiplexers and demultiplexers that provide 2-to-1 lane+rateconversion. For example, a lane multiplexer may accept two lanes (i.e.,two data streams) of PAM4 symbols and produce one lane (i.e., one datastream) of PAM4 symbols having twice the symbol rate of the input lanes.A corresponding lane demultiplexer would accept one input lane of PAM4symbols and produce two lanes of PAM4 symbols having half the symbolrate of the input lane. As another example, a lane multiplexer mayaccept two lanes (i.e., two bit streams) of NRZ bits and produce onelane (i.e., one bit stream) of NRZ bits having twice the bit rate of theinput lanes. A corresponding lane demultiplexer would accept one inputlane of NRZ bits and produce two lanes of NRZ bits having half thesymbol rate of the input lane.

PAM4-to-NRZ conversion can also be combined with lane+rate conversion,such that, e.g., one input lane of PAM4 symbols is converted into fouroutput lanes of NRZ bits having half the symbol rate of the input lane,and four input lanes of NRZ bits are converted into one output lane ofPAM4 symbols.

A memory 308 provides FIFO buffering between the transmitter andreceiver sets 302, 304. Note that the order of the converters 306 andthe memory 308 can be switched between the transmitter and receiver sets302, 304. A controller 310 coordinates the operation of the transmittersand receivers by, e.g., setting initial equalization parameters andensuring the training phase is complete across all lanes and linksbefore enabling the transmitters and receiver to enter the data transferphase.

Referring momentarily to FIG. 6, the PAM4-to-NRZ and/or 2-to-1 lane+rateconversion may conceptually be performed at the Data Link Layer 640,i.e., sandwiched between optional FEC and PCS sublayer processing by thePhysical Layers 622A, 622. In some variations, the transceiver may omitthe processing associated with some or all of the MAC, Reconciliation,PCS, and FEC Sublayers, performing the bit-to-lane remapping to bridgebetween lower sublayers such as FEC or even PMA. In some embodiments,the FEC sublayer is implemented on just the host-facing side or just thecable-facing side. In other embodiments, the bit-to-lane remapping isperformed to bridge between FEC sublayers on both sides.

FIG. 3B is a function block diagram of an illustrative transceiver thatomits the gearbox functionality, but includes the other componentsdescribed above. The transceiver embodiment of FIG. 3B has the samenumber of lanes in each direction (host-facing and cable-facing) usingthe same signaling formation (PAM4 or NRZ), whereas the embodiment ofFIG. 3A changes the signaling formation and provides twice as many lanesin one direction as the other.

In at least some contemplated embodiments, the host-facing set oftransmitters and receivers employs fixed equalization parameters thatare cable-independent, i.e., they are not customized on a cable-by-cablebasis. The cable-facing set of transmitters and receivers preferablyemploys cable-dependent equalization parameters that are customized on acable-by-cable basis. The cable-dependent equalization parameters may beadaptive or fixed, and initial values for these parameters may bedetermined during manufacturer tests of the cable. The equalizationparameters may include filter coefficient values for pre-equalizerfilters in the transmitters, and gain and filter coefficient values forthe receivers.

FIGS. 4 and 5 are block diagrams of an illustrative receiver and anillustrative transmitter that may be used to implement the sets 302,304. In FIG. 4, receiver 400 receives an analog electrical signal(CH_IN) and supplies it to a low noise amplifier (LNA) 402. The LNA 402provides a high input impedance to minimize channel loading andamplifies the received electrical signal to drive the input of acontinuous time linear equalizer (CTLE) filter 404. CTLE 404 providescontinuous time filtering to shape the signal spectrum to reduce thelength of the channel impulse response while minimizing leadinginter-symbol interference (ISI). A decision feedback equalizer (DFE) 406operates on the filtered signal to correct for trailing ISI and detecteach transmitted channel bit or symbol, thereby producing a demodulateddigital data stream. Some embodiments employ oversampling. A clock anddata recovery (CDR) circuit 408 extracts a clock signal from thefiltered signal and/or the digital data stream and supplies it to DFE406 to control sample and symbol detection timing. A serial-to-parallelcircuit 410 groups the digital data stream bits or symbols into blocksto enable the use of lower clock rates for subsequent on-chipoperations. The symbols or data blocks are placed on the digital receivebus (RXD) for retransmission to the remote end node by a transmitter.

While certain contemplated cable embodiments do not supportauto-negotiation, other contemplated embodiments do supportauto-negotiation in accordance with the Ethernet standard. Whensupported, the auto-negotiation may be implemented as described inPCT/CN2017/075961, titled “Ethernet link extension method and device” byinventors Yifei Dai, Haoli Qian, and Jeff Twombly, and filed 2017 Mar.8. A detector or packet information extractor 442 monitors the receivesignal for the end of the auto-negotiation phase and/or the beginning ofthe training phase frames.

During the training phase, a filter adaptation circuit 440 measures anerror between the input and output of a decision element in DFE 406,employing that error in accordance with well-known techniques from theliterature on adaptive filtering to determine adjustments for thecoefficients in CTLE filter 404, DFE 406, and a transmit filter 506(discussed further below), and to determine whether convergence has beenachieved. The locally-generated information (LOCAL_INFO) including thetransmit filter coefficient adjustments and the convergence status areprovided to the local transmitter 500 that communicates in the reversedirection on the data lane. As discussed below, the local transmittercommunicates the transmit filter adjustments and the convergence statusvia a back-channel to the source of the CH_IN signal. In that vein, thereceived signal includes back-channel information from the source of theCH_IN signal. A packet information extractor 442 detects theback-channel information (BACK_INFO) and passes it to the localtransmitter. Once convergence is achieved, receiver 400 is ready tobegin normal operations.

In FIG. 5, transmitter 500 receives blocks of channel bits or symbolsfor transmission to the source of the CH_IN signal (FIG. 4). Duringnormal operations, multiplexer 502 supplies blocks of channel bits orsymbols from the remote source (received on the TXD bus) to the parallelto serial (P2S) circuit 504. P2S circuit converts the blocks into adigital data stream. A transmit filter 506, also called a pre-emphasisfilter, converts the digital data stream into an analog electricalsignal with spectral shaping to combat channel degradation. Driver 508amplifies the analog electrical signal to drive the channel output(CH_OUT) node.

If supported, the auto-negotiation phase may be implemented as set forthin Y. Dai et al. During the training phase, multiplexer 502 obstructsinformation from the TXD bus, instead supplying P2S circuit 504 withtraining frames from a training controller 540. The training controller540 generates the training frames based on the convergence status andtransmit filter coefficient adjustments (LOCAL_INFO) received from thelocal receiver 400. That is, in addition to training patterns, thetraining frames include backchannel information to be used by the remoteend of the channel. Note that even after the local receiver indicatesfilter convergence has occurred, the training controller 540 may prolongthe training phase to coordinate training phase timing across lanes andalong each link of the channel. The training frames include trainingsequences as specified by the relevant portions of the current Ethernetstandard (IEEE Std 802.3).

The training controller 540 further accepts the back-channel information(BACK_INFO) extracted by the local receiver from received trainingframes sent by the local end node. The training controller applies thecorresponding adjustments to the coefficients of transmit filter 506.Upon conclusion of the training phase, multiplexer 502 begins forwardingTXD blocks to the P2S circuit 504.

FIG. 6 is an architecture diagram of the network interface of a hostdevice 602 and a cable connector 102 having one of the illustrativetransceivers discussed previously. The architecture is expressed interms of the ISO/IEC Model for Open Systems Interconnection (See ISO/IEC7498-1:1994.1) for communications over a physical medium such asconductors 106. The interconnection reference model employs a hierarchyof layers with defined functions and interfaces to facilitate the designand implementation of compatible systems by different teams or vendors.While it is not a requirement, it is expected that the higher layers inthe hierarchy will be implemented primarily by software or firmwareoperating on programmable processors while the lower layers may beimplemented as application-specific integrated circuits orsimilarly-dedicated hardware.

The Application Layer 608 is the uppermost layer in the model, and itrepresents the user applications or other software operating ondifferent systems that need a facility for communicating messages ordata. The Presentation Layer 610 provides such applications with a setof application programming interfaces (APIs) that provide formal syntaxalong with services for data transformations (e.g., compression),establishing communication sessions, connectionless communication mode,and negotiation, to enable the application software to identify theavailable service options and select therefrom. The Session Layer 612provides services for coordinating data exchange including: sessionsynchronization, token management, full- or half-duplex modeimplementation, and establishing, managing, and releasing a sessionconnection. In connectionless mode, the Session Layer may merely mapbetween session addresses and transport addresses.

The Transport Layer 614 provides services for multiplexing, end-to-endsequence control, error detection, segmenting, blocking, concatenation,flow control on individual connections (including suspend/resume), andimplementing end-to-end service quality specifications. The focus of theTransport Layer 614 is end-to-end performance/behavior. The NetworkLayer 616 provides a routing service, determining the links used to makethe end-to-end connection and when necessary acting as a relay serviceto couple together such links. The Data link layer 618 serves as theinterface to physical connections, providing delimiting,synchronization, sequence and flow control across the physicalconnection. It may also detect and optionally correct errors that occuracross the physical connection. The Physical layer 622 provides themechanical, electrical, functional, and procedural means to activate,maintain, and deactivate channels, and to use the channels fortransmission of bits across the physical media 106.

The Data Link Layer 618 and Physical Layer 622 are subdivided andmodified slightly by IEEE Std 802.3-2015, which provides a Media AccessControl (MAC) Sublayer 620 in the Data Link Layer 618 to define theinterface with the Physical Layer 622, including a frame structure andtransfer syntax. Within the Physical Layer 622, the standard provides avariety of possible subdivisions such as the one illustrated in FIG. 6,which includes an optional Reconciliation Sublayer 624, a PhysicalCoding Sublayer (PCS) 626, a Forward Error Correction (FEC) Sublayer628, a Physical Media Attachment (PMA) Sublayer 630, a Physical MediumDependent (PMD) Sublayer 632, and an Auto-Negotiation (AN) Sublayer 634.

The optional Reconciliation Sublayer 624 merely maps between interfacesdefined for the MAC Sublayer 620 and the PCS Sublayer 626. The PCSSublayer 626 provides scrambling/descrambling, data encoding/decoding(with a transmission code that enables clock recovery and bit errordetection), block and symbol redistribution, PCS alignment markerinsertion/removal, and block-level lane synchronization and deskew. Toenable bit error rate estimation by components of the Physical Layer622, the PCS alignment markers typically include Bit-Interleaved-Parity(BIP) values derived from the preceding bits in the lane up to andincluding the preceding PCS alignment marker.

The FEC Sublayer 628 provides, e.g., Reed-Solomon coding/decoding thatdistributes data blocks with controlled redundancy across the lanes toenable error correction. In some embodiments (e.g., in accordance withArticle 91 or proposed Article 134 for the IEEE Std 802.3), the FECSublayer 628 modifies the number of lanes (Article 91 provides for a20-to-4 lane conversion).

The PMA Sublayer 630 provides lane remapping, symbol encoding/decoding,framing, and octet/symbol synchronization. The PMD Sublayer 632specifies the transceiver conversions between transmitted/receivedchannel signals and the corresponding bit (or digital symbol) streams.An optional AN Sublayer 634 is shown here as a internal element of thePMD Sublayer 632, and it implements an initial start-up of thecommunications channels to conduct an auto-negotiation phase and alink-training phase before entering a normal operating phase. Theauto-negotiation phase enables the end nodes to exchange informationabout their capabilities, and the training phase enables the end nodesto adapt both transmit-side and receive-side equalization filters in afashion that combats the channel non-idealities.

A receptacle 636 is also shown as part of the PMD sublayer 632 torepresent the physical network interface port. The connector 102 has aplug that mates with the receptacle 636 of the host device 602. Withinthe connector, the transceiver may implement a host-facing PhysicalLayer 622A, a cable-facing Physical Layer 622B, and a Data Link Layer640 that bridges together the two Physical Layers.

The MAC, Reconciliation, PCS, FEC, PMA, and PMD Sublayers, may beimplemented as application-specific integrated circuitry to enablehigh-rate processing and data transmission. The receiver and transmittersets 302, 304, may implement the PMA and PMD sublayers. More informationregarding the operation of the various layers and sublayers, as well asthe electrical and physical specifications of the connections betweenthe nodes and the communications medium (e.g., pin layouts, lineimpedances, signal voltages & timing), and the electrical and physicalspecifications for the communications medium itself (e.g., conductorarrangements in copper cable, limitations on attenuation, propagationdelay, signal skew), can be found in the current Ethernet standard andproposed updates thereto, and any such details should be considered tobe well within the knowledge of those having ordinary skill in the art.

FIG. 7 is a flowchart of an illustrative cable manufacturing method. Itbegins in block 702 with connecting the electrical conductors betweenthe unary end connector and the split end connectors, typically bysoldering the wire ends to pads of circuit boards attached to theconnector plugs. Traces on the circuit board may directly connect thepads to the pins of the connector plug. Alternatively, the traces mayconnect a chip with an integrated circuit transceiver or redriverbetween the pads and the pins of the connector plug. This and theensuing steps may be performed by automated manufacturing/testingequipment. In block 704, the equipment packages the circuit boards(including any integrated circuit components) in a respective endconnector for the network cable. The connectors are adapted to mate withnetwork interface ports of host devices, and include plugs thatelectrically connect with matching receptacles in the ports.

In block 706, the equipment tests the cable to verify compliance withperformance specifications and to determine cable-dependent equalizationparameters for use by the cable-facing transmitter and receiver sets. Inblock 708, the equipment causes the transceivers to store theequalization parameters (including both cable-dependent andcable-independent parameters) in nonvolatile memory. The cable may thenbe packaged and sold to customers.

Though the foregoing description has focused mainly on a 1:4 breakoutcable design, the disclosed principles are also applicable to othercable designs, including 1:2, 1:8, and 1:16 breakout cable designs. Each100 Gbps PAM4 lane may transport PAM4 symbols at 53.125 Gbaud. Each 50Gbps PAM4 may transport PAM4 symbols at 26.5625 Gbaud, while each 25Gbps NRZ lane may transport NRZ symbols at 26.5625 Gbaud. The lanes canbe ganged together in accordance with the Ethernet standard to provide25 Gbps, 50 Gbps, 100 Gbps, 200 Gbps, 400 Gbps, or 800 Gbps. Otherstandards can also be supported, with the connector transceiversproviding in-line format conversion and lanemultiplexing/demultiplexing.

Numerous alternative forms, equivalents, and modifications will becomeapparent to those skilled in the art once the above disclosure is fullyappreciated. It is intended that the claims be interpreted to embraceall such alternative forms, equivalents, and modifications that areencompassed in the scope of the appended claims.

What is claimed is:
 1. An active 1:N breakout cable that comprises: aunary end connector connected by electrical conductors to each of Nsplit end connectors, N being an integer greater than 1, the unary endconnector being adapted to fit into a network interface port of aprimary host device to provide output PAM4 electrical signals thatconvey a multi-lane outbound data stream to the primary host device andto accept input PAM4 electrical signals that convey multi-lane inbounddata stream from the primary host device, and each of the split endconnectors being adapted to fit into a network interface port of asecondary host device to provide output NRZ electrical signals thatconvey a split portion of the inbound data stream to that secondary hostdevice and to accept input NRZ electrical signals that convey a splitportion of the outbound data stream from that secondary host device,each of the split end connectors including a transceiver that performsclock and data recovery on the input NRZ electrical signals to extractand re-modulate the split portion of the outbound data stream as one ormore of converging transit signals that transport the split portions ofthe inbound data stream via the electrical conductors to the unary endconnector, wherein the transceiver performs clock and data recovery ondiverging transit signals to extract and re-modulate the split portionof the inbound data stream as said output NRZ electrical signals.
 2. Theactive 1:N breakout cable of claim 1, wherein the unary end connectorincludes a transceiver that performs clock and data recovery on theinput PAM4 electrical signals to extract and re-modulate the inbounddata stream as diverging transit signals that transport the splitportions of the inbound data stream via the electrical conductors to thesplit end connectors, and wherein the transceiver performs clock anddata recovery on converging transit signals to extract and re-modulatethe outbound data stream as said output PAM4 electrical signals.
 3. Theactive 1:N breakout cable of claim 2, wherein the diverging transitsignals and the converging transit signals are NRZ electrical signals.4. The active 1:N breakout cable of claim 3, wherein the transceiver inthe unary end connector further performs forward error correction whenextracting the outbound data stream.
 5. The active 1:N breakout cable ofclaim 3, wherein the transceiver in each split end connector furtherperforms forward error correction when extracting the split portion ofthe inbound data stream.
 6. The active 1:N breakout cable of claim 1,wherein the diverging transit signals and the converging transit signalsare PAM4 electrical signals.
 7. The active 1:N breakout cable of claim6, wherein the unary end connector includes a transceiver that performsclock and data recovery on the input PAM4 electrical signals to extractand re-modulate the inbound data stream as the diverging transit signalsthat transport the split portions of the inbound data stream via theelectrical conductors to the split end connectors, and wherein thetransceiver in the unary end connector performs clock and data recoveryon the converging transit signals to extract and re-modulate theoutbound data stream as said output PAM4 electrical signals.
 8. Theactive 1:N breakout cable of claim 7, wherein the transceiver in theunary end connector further performs forward error correction whenextracting the outbound data stream.
 9. An active 1:N breakout cablethat comprises: a unary end connector connected by electrical conductorsto each of N split end connectors, N being an integer greater than 1,the unary end connector being adapted to fit into a network interfaceport of a primary host device to provide output PAM4 electrical signalsthat convey a multi-lane outbound data stream to the primary host deviceand to accept input PAM4 electrical signals that convey multi-laneinbound data stream from the primary host device, and each of the splitend connectors being adapted to fit into a network interface port of asecondary host device to provide output NRZ electrical signals thatconvey a split portion of the inbound data stream to that secondary hostdevice and to accept input NRZ electrical signals that convey a splitportion of the outbound data stream from that secondary host device,wherein the unary end connector includes a transceiver that performsclock and data recovery on the input PAM4 electrical signals to extractand re-modulate the inbound data stream as diverging transit signalsthat transport the split portions of the inbound data stream via theelectrical conductors to the split end connectors, and wherein thetransceiver performs clock and data recovery on converging transitsignals to extract and re-modulate the outbound data stream as saidoutput PAM4 electrical signals, wherein the diverging transit signalsand the converging transit signals are NRZ electrical signals, whereineach of the split end connectors includes a redriver circuit thatprovides the output NRZ electrical signals by amplifying the divergingtransit signals that it receives, and wherein the redriver circuitprovides at least one of the converging transit signals by amplifyingthe input NRZ electrical signals that it receives.
 10. A cablemanufacturing method that comprises: packaging a transceiver into aunary end connector that is adapted to mate with a network interfaceport of a primary host device, the transceiver being configured toprovide output PAM4 electrical signals that convey a multi-lane outbounddata stream to the primary host device and to accept input PAM4electrical signals that convey multi-lane inbound data stream from theprimary host device; connecting each of N split end connectors to theunary end connector with electrical conductors, where N is an integergreater than one, and where each of the split end connectors is adaptedto mate with a network interface port of a secondary host device toprovide output NRZ electrical signals that convey a split portion of theinbound data stream to that secondary host device and to accept inputNRZ electrical signals that convey a split portion of the outbound datastream from that secondary host device, the transceiver in the unary endconnector being configured to perform clock and data recovery on theinput PAM4 electrical signals to extract and re-modulate the inbounddata stream as diverging transit signals that transport the splitportions of the inbound data stream via the electrical conductors to thesplit end connectors, and further configured to perform clock and datarecovery on converging transit signals to extract and re-modulate theoutbound data stream as said output PAM4 electrical signals; andpackaging a transceiver in each of the split end connectors, thetransceiver in each split end connector being configured to performclock and data recovery on the diverging transit signals that itreceives to extract and re-modulate the split portion of the inbounddata stream, and being further configured to perform clock and datarecovery on the input NRZ electrical signals to extract and re-modulatethe split portion of the outbound data stream, wherein the divergingtransit signals and the converging transit signals are PAM4 electricalsignals.
 11. A cable manufacturing method that comprises: packaging atransceiver into a unary end connector that is adapted to mate with anetwork interface port of a primary host device, the transceiver beingconfigured to provide output PAM4 electrical signals that convey amulti-lane outbound data stream to the primary host device and to acceptinput PAM4 electrical signals that convey multi-lane inbound data streamfrom the primary host device; connecting each of N split end connectorsto the unary end connector with electrical conductors, where N is aninteger greater than one, and where each of the split end connectors isadapted to mate with a network interface port of a secondary host deviceto provide output NRZ electrical signals that convey a split portion ofthe inbound data stream to that secondary host device and to acceptinput NRZ electrical signals that convey a split portion of the outbounddata stream from that secondary host device; and packaging a redrivercircuit into each of the split end connectors, the redriver circuitbeing configured to provide the output NRZ electrical signals byamplifying the diverging transit signals that it receives, and beingfurther configured to provide at least one of the converging transitsignals by amplifying the input NRZ electrical signals that it receives,the transceiver in the unary end connector being configured to performclock and data recovery on the input PAM4 electrical signals to extractand re-modulate the inbound data stream as diverging transit signalsthat transport the split portions of the inbound data stream via theelectrical conductors to the split end connectors, and furtherconfigured to perform clock and data recovery on converging transitsignals to extract and re-modulate the outbound data stream as saidoutput PAM4 electrical signals, wherein the diverging transit signalsand the converging transit signals are NRZ electrical signals.
 12. Acable manufacturing method that comprises: packaging a transceiver intoa unary end connector that is adapted to mate with a network interfaceport of a primary host device, the transceiver being configured toprovide output PAM4 electrical signals that convey a multi-lane outbounddata stream to the primary host device and to accept input PAM4electrical signals that convey multi-lane inbound data stream from theprimary host device; connecting each of N split end connectors to theunary end connector with electrical conductors, where N is an integergreater than one, and where each of the split end connectors is adaptedto mate with a network interface port of a secondary host device toprovide output NRZ electrical signals that convey a split portion of theinbound data stream to that secondary host device and to accept inputNRZ electrical signals that convey a split portion of the outbound datastream from that secondary host device; and packaging a transceiver intoeach of the split end connectors, the transceiver in each split endconnector being configured to perform clock and data recovery on thediverging transit signals that it receives to extract and re-modulatethe split portion of the inbound data stream, and being furtherconfigured to perform clock and data recovery on the input NRZelectrical signals to extract and re-modulate the split portion of theoutbound data stream, the transceiver in the unary end connector beingconfigured to perform clock and data recovery on the input PAM4electrical signals to extract and re-modulate the inbound data stream asdiverging transit signals that transport the split portions of theinbound data stream via the electrical conductors to the split endconnectors, and further configured to perform clock and data recovery onconverging transit signals to extract and re-modulate the outbound datastream as said output PAM4 electrical signals, wherein the divergingtransit signals and the converging transit signals are NRZ electricalsignals.